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Publications

 

Journal Papers

  • J.   Shappir  and  A.Kolodny,  "The  Response  of  Small Photovoltaic  Detectors  to Uniform Radiation,” IEEE Transactions  on  Electron Devices, Vol. ED-24, pp.1093-1098, 1977. pdf
  • T.   Bernstein  and  A. Kolodny,  "A  Useful  Method  for Approximating  the  Profile  of  Ions  Implanted through a Thin  Film,”  IEEE  Trans. on  Electron   Devices,   Vol. ED-24, pp.1365-1366, 1977.  pdf
  • A.  Kolodny  J. Shappir,  "Diffusion  Properties  of Cadmium  in InSb,” Journal of the Electrochemical Society, Vol.125, no. 9, pp.1530-1534, 1978.  pdf
  • A.  Kolodny,  "Current  Gain  of  Shallow-Junction  Lateral  Transistors,”  IEEE  Transactions  on Electron Devices, Vol.  ED-26,  pp.987-989, 1979.   pdf
  • A.  Kolodny and I.  Kidron,  "Properties  of  Ion-Implanted  Junctions   in   Mercury-Cadmium-Telluride,”  IEEE  Transactions  on  Electron Devices, Voand  l.  ED-27, pp.37-43, 1980. pdf
  • A.   Kolodny,  Y.J.    Shacham-Diamand   and  I. Kidron, "N-Channel  MOS Transistors in Mercury-Cadmium-Telluride,” IEEE Transactions  on Electron Devices, Vol.  ED-27, pp.591-595, 1980. pdf
  • J.   Shappir,  A.   Kolodny  and  Y.J.    Shacham-Diamand, "Diffusion  Profiling Using the Graded C-V Method,” IEEE Transactions on Electron Devices, Vol.  ED-27, p.993, 1980. pdf
  • D.   Lubzens,  A.   Kolodny  and  Y.   Shacham,  "Automated  Measurement  and  Analysis  of MIS Interfaces in Narrow-Bandgap  Semiconductors,” IEEE Transactions on Electron Devices, Volume 28,  Issue 5,  pp. 546 – 551, 1981. pdf
  •  A.  Kolodny and I. Kidron,  "Two-dimensional  Effects  in  Intrinsinc Photo-Conductive Infrared  Detectors,”  Infrared  Physics, Vol.  22, pp.9-22, 1982. pdf
  • B.  Eitan and A.  Kolodny, "Two  Components  of  Tunneling  Current  in  MOS  Structures,” Applied  Physics  Letters, Vol.  43, pp.106-108, 1983.  pdf
  • A. Kolodny,  S.   Nieh,  B.   Eitan  and  J. Shappir,  "Analysis  and  Modeling  of Floating-gate EEPROM Cells,” IEEE  Transactions on Electron Devices, Volume 33,  Issue 6,  pp. 835 – 844,  1986.  pdf
  • Y. Elboim, R. Ginosar and A. Kolodny, “A Clock Tuning Circuit for  System on Chip,”   IEEE Transactions on VLSI, vol. 11, pp.616-626, 2002.   pdf
  • O. Milter and A. Kolodny, “Crosstalk Noise Reduction in Synthesized Digital  Logic Circuits,”  IEEE Transactions on VLSI , Volume: 11, pp. 1153 – 1158, Dec. 2003.    pdf
  • E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “QNoC: QoS architecture and  design process for cost-effective Network on Chip,”  Special issue on  Networks on Chip,  The Journal of Systems Architecture, Volume 50, pp. 105-128, February 2004.  pdf
  • E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny , “Cost considerations in Network on Chip" , Special issue on Networks on Chip, Integration – the  VLSI journal, Vol. 38, No. 1, pp. 19-42, Oct. 2004. pdf
  • N. Dolev, A. Kornfeld and A. Kolodny, “Comparison of Sigma-Delta Converter Circuit Architectures in Digital CMOS Technology,”  Journal of Circuits, Systems and Computers, vol. 14, No. 3, pp.1-18, 2005.   pdf
  • T. Morad, U. Weiser, A. Kolodny, M. Valero and E. Ayguade,   “Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors,” IEEE Computer Architecture Letters, vol. 4,  2005.  pdf
  • M. Moreinis, A. Morgenshtein, I. Wagner and A. Kolodny, “Logic gates as  Repeaters,” IEEE Transactions on VLSI, Volume 14, pp.1276 – 1281, Nov. 2006.   pdf
  • S. Wimer, S. Michaely, K. Moiseev and A. Kolodny,  “Optimal Bus Sizing in  Migration of Processor Design,”  IEEE Transactions  on Circuits and Systems I, Volume 53,  Issue 5, pp. 1089 – 1100, May 2006. pdf
  • M. Behar, A. Mendelson and A. Kolodny, “Trace Cache Sampling Filter,”  ACM Transactions on Computer Systems, 25, 1 (Feb. 2007), 3.  pdf
  • Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "Network Delays and Link Capacities in Application-Specific Wormhole NoCs," VLSI Design Special issue on Networks on Chip, 2007.  pdf
  • Z. Guz, I. Keidar, A. Kolodny and U. C. Weiser, "Nahalal: Memory Organization for Chip Multiprocessors", IEEE Computer architecture letters, June 2007.   pdf
  • K. Moiseev, S. Wimer and A. Kolodny, “On optimal ordering of signals in parallel wire bundles,” Integration – the VLSI Journal, Vol. 41, 2008, pp. 253 – 268. pdf
  • M. Popovich, M. Sotman, A. Kolodny and E. G. Friedman, “Effective Radii of On-Chip Decoupling Capacitors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 16, No. 7, pp.894-907, July 2008. pdf
  • M. Popovich, E. G. Friedman, M. Sotman and A. Kolodny, “On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 7, pp.908-921, July 2008. pdf
  • K. Moiseev, A. Kolodny and S. Wimer, “Timing-Aware Power-Optimal Ordering of Signals,” ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 4, Article 65, Sept. 2008. pdf
  • R. Dobkin, R. Ginosar, and A. Kolodny, “QNoC Asynchronous Router," Integration , the VLSI Journal, Vol. 42, pp.103-115, February 2009. pdf
  • I. Walter, I. Cidon, and A. Kolodny, "BENOC: A bus enhanced NoC", IEEE CAL, Volume 7, Issue 1, 2008.   pdf
  • K. Moiseev, A. Kolodny and S. Wimer, “Power-Delay Optimization in VLSI Microprocessors by Wire Spacing,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 4 (August 2009), Article No. 55, 2009, ISSN: 1084-4309. pdf
  • Z. Guz, E. Bolotin, I. Keidar, A. Kolodny, A. Mendelson and U. Weiser, Many-Core vs. Many-Thread Machines: Stay Away From the Valley", IEEE Computer Architecture Letters, Volume 8,  Issue 1,  Jan. 2009. pdf
  • A. Morgenshtein, E. G. Friedman, R. Ginosar and A. Kolodny, "Unified Logical Effort – A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 5, pp. 689-696, May 2010. (TVLSI 2012 Best Paper Award)   pdf
  • R. Dobkin, R. Ginosar, A. Kolodny and M. Moyal, "Asynchronous Current Mode Serial Communication," IEEE Transactions on VLSI systems, to appear in September 2010. pdf
  • K. Moiseev, A. Kolodny and S. Wimer, "Interconnect Bundle Sizing under Discrete Design Rules", accepted to IEEE Transactions on Computer Aided Design, 2010. pdf
  • K. Moiseev, A. Kolodny and S. Wimer, "The Complexity of VLSI Power-Delay Optimization by Interconnect resizing", accepted to Journal of Combinatorial Optimization, 2010. pdf
  • E. Krimer, M. Erez, I. Keslassy, A. Kolodny and I. Walter, "Static Timing Analysis for Modeling QoS in Networks on Chip", Journal of Parallel and Distributed Computing  (5): 687-699 (2011). pdf
  • P. Gelsinger, D. Kirkpatrick, A. Kolodny and G. Singer, "Such a CAD!," IEEE Solid-State Circuits Magazine, vol.2, no.3, pp.32-43, Summer 2010.  pdf
  • I. Vaisband, E. G. Friedman, R. Ginosar and A. Kolodny, "Low Power Clock Network Design,"  J. Low Power Electron. Appl. , 2010. pdf
  •  R. Manevich, I. Cidon, A. Kolodny, and W. Isask'har, "Centralized Adaptive Routing for NoCs," Computer Architecture Letters , vol.9, no.2, pp.57-60, Feb. 2010. pdf
  • S. Wimer, K. Moiseev and A. Kolodny, "On VLSI Interconnect Optimization and Linear Ordering Problem", accepted to Optimization and Engineering, 2011. pdf
  • Y. Aizik and A. Kolodny, "Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints," VLSI Design, 2011. pdf
  • Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez, “Static timing analysis for modeling QoS in networks-on-chip,”  J. Parallel Distrib. Comput. 71(5): 687-699 (2011). pdf
  • T.Y. Morad, A. Kolodny and U.C. Weiser, “Task Scheduling Based On Thread Essence and Resource Limitations,” accepted to Journal of Computers, Vol. 7, Issue 1, 2012. pdf
  • K. Moiseev, A. Kolodny and S. Wimer, “The complexity of VLSI power-delay optimization by interconnect resizing,”  Journal of Combinatorial Optimization, Volume 23, Issue 2 (2012), pp. 292-300. pdf
  • V. Vishnyakov, E.G. Friedman and A. Kolodny, “Multi-Aggressor Capacitive and Inductive Coupling Noise  - Modeling and Mitigation”,  Microelectronics Journal  Vol. 43 (2012), pp. 235-243. pdf
  • R. Malits, E. Bolotin, A. Kolodny and A. Mendelson, “Exploring the Limits of GPGPU Scheduling,” ACM Transactions on Architecture and Code Optimization (TACO)  8(4): 29 (2012). pdf
  • E. Zahavi, I. Cidon and A. Kolodny, "GANA: A Novel Low Cost Conflict Free NoC Architecture," ACM Transactions on Embedded computing systems 12(4): 109 (2013). pdf
  • A. Abdelhadi, R. Ginosar, A. Kolodny,  E. G. Friedman, “Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks,”  Integration, the VLSI Journal, Volume 46, Issue 4, Pages 382-391, September 2013. pdf
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM – ThrEshold Adaptive Memristor Model,"  accepted to IEEE Transactions on Circuits and Systems I: Regular Paper,Vol. 60, No. 1, pp. 211-221, 2013. pdf
  • E. Zahavi, I. Keslassy and A. Kolodny, "Distributed| Adaptive Routing Convergence to Non-Blocking Data Center Network Routing Assignments", accepted to  IEEE JSAC – Switching and| Routing for Scalable and Energy-efficient Datacenter Networks, 2013. pdf
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "The Desired Memristor for Circuit Designers," IEEE Circuits and Systems Magazine, second quarter, pp. 17-22, May 2013. pdf
  • S. kvatinsky, Y. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, U. Weiser, "Memristor-Based Multithreading," IEEE Computer Architecture Letters, 2013.  pdf
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based Material Implication (IMPLY) Logic: Design Principles and Methodologies," IEEE Transactions on Very Large Scale Integration (TVLSI),  Vol. 22, No. 10, pp. 2054-2066, October 2014. pdf
  •  R. Patel, S. Kvatinsky, E. G. Friedman, and A. Kolodny, “Multistate Register Based on Resistive RAM,” Accepted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014pdf
  • Y. Levy, J. Bruck, Y. Cassuto, E. G. Friedman, A. Kolodny, E. Yaakobi, and S. Kvatinsky, “Logic Operations in Memory Using a Memristive Akers Array,”  Microelectronics Journal,  45 (2014), pp. 1429-1437. pdf
  • R. Manevich, L. Polishuk, I. Cidon and A. Kolodny, “Designing Single-Cycle Long Links in Hierarchical NoCs”, Microprocessors and Microsystems, Vol. 38, November 2014, pp. 814-825. pdf
  • S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, “MAGIC – Memristor Aided LoGIC,”  ,"  IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 895-899,  2014. pdf
  •  K. Moiseev, A. Kolodny, and S. Wimer, "Timing-constrained Power Minimization in VLSI Circuits by Simultaneous Multilayer Wire Spacing", Integration, Volume 48, January 2015, pp. 116-128. pdf
  • Y. Ben-Itzhak, M. Shabun,  N. Shmuel, I. Cidon, and A. Kolodny,  “Heterogeneous NoC Router Architecture”, accepted to  IEEE Transactions on Parallel and Distributed Systems, 2014. pdf
  • D. Soudry, S. Kvatinsky, D. Di Castro, A. Gal, E. G. Friedman, and A. Kolodny, "Hebbian Learning Rules with Memristors,"  accepted to IEEE Transactions on Neural Networks and Learning (TNNLS), 2014. 
  •  S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, "VTEAM – A General Model for Voltage Controlled Memristor," Transactions on Circuits and Systems II: Express Briefs, volume 62, August 2015, pp. 786-790. 
  • Y. Ben-itzhak, I. Cidon and A. Kolodny, "Latency Evaluation of Heterogeneous Wormhole NoCs," accepted to Integration, 2014.
  •  R. Manevich, I. Cidon, A. Kolodny, "Design and Dynamic Management of Hierarchical NoCs", accepted to Microprocessors and Microsystems, 2015. 
  •  Morad, T.Y.; Shomron, G.; Erez, M.; Kolodny, A.; Weiser, U., "Optimizing Read-Once Data Flow in Big-Data Applications," Computer Architecture Letters , no.99, pp.1-1. doi: 10.1109/LCA.2016.2520927.   
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Conference Papers

  • A. Kolodny and J. Shappir, “Lateral effects in photodiodes,” Proceedings of ESSDRC, 1977; Also: IEEE Israel conference 1977.
  • A.  Kolodny, R.  Friedman and  T.   Ben-Tzur,  "Rule-based Static  Debugger  and Simulation Compiler for VLSI Schematics,” Proceedings  of   1985   IEEE International   Conference   on  Computer-Aided Design (ICCAD), Santa Clara, CA, Nov.  1985.
  • Y. Elboim, A. Kolodny, R. Ginosar,  “A Clock Tuning Circuit for IP Core Integration in SoC,” International workshop on IP-based synthesis and SoC  design,  Grenoble, France, Dec. 2000.
  • Y. Elboim, A. Kolodny, R. Ginosar,  “A Clock Tuning Circuit for IP Core Integration in SoC,” Proc. DesigCon 2001, January 2001, Santa Clara, CA.
  • O. Kosyakovsky, A.  Mendelson and A. Kolodny,. “The use of profile-based  trace classification for improving the power and performance of trace cache systems,” 4th Workshop on  Feedback-Directed and Dynamic Optimization  (FDDO-4), Austin, Texas, December 2001.  pdf
  • Y. Elboim, R. Ginosar and A. Kolodny, “A Clock Tuning circuit for System on  Chip,” ACiD-WG 2002 Workshop, Munich, Germany, January 2002.
  • O. Milter and A. Kolodny, “Crosstalk Delay Analysis and    Prevention Using  PrimeTime SI and Design Compiler in High  Frequency CPU Design,” Proc. SNUG, Boston, Mass., September 2002.
  • Y. Elboim, R. Ginosar and A. Kolodny, “A Clock Tuning  Circuit for System on  Chip,” Proceedings of ESSCIRC 2002, Florence, Italy, September 2002. pdf
  • A. Khamaisee, A. Mendelson and A. Kolodny, “Can hot traces help value prediction?,” 1st Value-prediction workshop,  San Diego, CA, June 2003. pdf
  • A. Morgenshtein, M. Moreinis, I. Wagner and A. Kolodny, “Logic gates as Repeaters,” Proceedings of IFIP conference on VLSI-SoC , Darmstadt,  Germany, December 2003. pdf
  • N. Magen, A. Kolodny, U. Weiser and N. Shamir,  “ Interconnect-power dissipation in a  Microprocessor,”  International System Level Interconnect   Prediction workshop (SLIP 2004), Paris, February 2004.  pdf
  • A. Morgenshtein, I. Cidon, A. Kolodny and R. Ginosar, “Comparative analysis of serial vs. parallel lings in NoC,”  Proceedings of 2004 International Symposium on System-on-Chip, pp. 185 – 188,  Tampere, Finland, November 2004. pdf
  • M. Moreinis, A. Morgenshtein, I. A. Wagner and A.   Kolodny, “Repeater Insertion combined with LGR Methodology for on-Chip  Interconnect Timing Optimization,”  IEEE International Conference on  Electronics, Circuits and Systems, Tel Aviv, December 2004.  pdf
  • Michaely, S.l Wimer, and A. Kolodny, “Optimal Resizing of Bus Wires in Layout Migration,” Proceedings of 11th IEEE International Conference on  Electronics, Circuits and Systems, Tel Aviv, December 2004.  pdf
  • A. Barger, D. Goren and A. Kolodny, “Design and Modeling   of Network on Chip Interconnects,” IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, December 2004. pdf
  • E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “Automatic and Hardware-Efficient SoC Integration by QoS Network on Chip,” IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, December 2004. pdf
  • A. Morgenshtein, I. Cidon, A. Kolodny and R. Ginosar, “Micro-modem concept for communications in networks on chip,” IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, December 2004. pdf
  • F. Chu, A. Kolodny, S. Maital and  D. Perlmutter,  “The innovation paradox:  Reconciling creativity & discipline – How winning organizations combine inspiration with perspiration,” Proceedings of IEEE International Engineering Management Conference, vol. 3 pp. 949-953, Singapore, October 2004. pdf
  • A. Morgenshtein, I.Cidon, A. Kolodny and R. Ginosar, "Low-Leakage Repeaters for NoC Interconnects,” Proceedings of the IEEE International Symposium on Circuits and Systems 2005. pdf
  • M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, " On-Chip Power   Distribution  Grids with Multiple Supply Voltages for High Performance Integrated  Circuits,” Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 2-7, April 2005  (received best student paper award for GLSVLSI 2005). pdf
  • S. T. Morad, U. Weiser and A. Kolodny, “Why Not Data Trace Cache,”  Workshop on Duplicating, Deconstructing, and Debunking (WDDD, Held in conjunction with ISCA-32), 2005. pdf
  • M. Behar, A. Mendelson and A. Kolodny, “Trace Cache Sampling Filter,” 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 255 – 266, 17-21 Sept. 2005. pdf
  • M. Sotman, M..Popovich, A. Kolodny and E.G. Friedman, “Leveraging Symbiotic On-Die Decoupling Capacitance,” IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), October 2005. pdf
  • K. Moiseev, S. Wimer and A. Kolodny, “Timing Optimization of Interconnect by Simultaneous Net-Ordering, Wire Sizing and Spacing,” Proceedings of the IEEE International Symposium on Circuits and Systems 2006. pdf
  • I. Walter, Z. Guz, I. Cidon, R. Ginosar and A. Kolodny, “Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip,” Proceedings of Design Automation and Test in Europe (DATE 2006). pdf
  • R. Dobkin, R. Ginosar and A. Kolodny, " Fast Asynchronous Shift Register for Bit-Serial Communication," Proc. ASYNC 2006. pdf
  • M. Sotman, A. Kolodny, M. Popovich and E. Friedman, "On-die Decoupling Capacitance: Frequency Domain Analysis of Activity Radius," Proceedings of the IEEE International Symposium on Circuits and Systems 2006. pdf
  • M. Popovich, E.G. Friedman, M. Sotman, A. Kolodny and R.M. Secareanu, “Maximum effective distance of on chip Decoupling Capacitors in Power Distribution Grids,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 173 – 179, April/May 2006.  pdf
  • A. Barger, D. Goren and A. Kolodny, “Simple Criterion for Maximizing Data Rate in NoC Links”, 10th IEEE Workshop on Signal Propagation on Interconnects, Berlin, May 2006. (pdf)
  • A. Morgenshtein, A. Kolodny, R. Ginosar, "Link Division Multiplexing forNoC Links", IEEE 24th Convention of Electrical and Electronics Engineers in Israel, Israel, pp. 245-249, November 2006. pdf
  • A. Morgenshtein, A. Kolodny, R. Ginosar, "Asynchronous Bit-stream Compression. ",  IEEE 24th Convention of Electrical and Electronics Engineers in Israel, Israel, pp. 241-244, November 2006. pdf
  • K. Moiseev, S. Wimer  and A. Kolodny, "An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design", IEEE 24th Convention of Electrical and Electronics Engineers in Israel, Israel, November 2006. pdf
  • R. Dobkin, Y. Perelman, T. Liran, R. Ginosar and A. Kolodny, "High rate wave-pipelined asynchronous on-chip bit-serial data link", Accepted to ASYNC 2007. pdf
  • E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "Routing Table Minimization for Irregular Mesh NoCs", DATE 2007,Nice, France, March 2007.  pdf
  • E. Bolotin, Z. Guz, I. Cidon, R. Ginosar and A. Kolodny, "The Power of Priority: NoC based Distributed Cache Coherency", NOCS 2007, Princeton, NJ, May 2007.  pdf
  • Walter, I. Cidon, R. Ginosar and A. Kolodny, "Access regulation to Hot-Modules in Wormhole Networks", NOCS 2007, Princeton, NJ, May 2007. pdf
  • Dobkin, Y. Perelman, T. Liran, R. Ginosar, and A. Kolodny, “High rate wave-pipelined asynchronous on-chip bit-serial data link,” Thirteenth IEEE International Symposium on Asynchronous Circuits and Systems, Berkeley, USA, March 2007. pdf
  • A. Morgenshtein, E. G. Friedman, R. Ginosar, and A. Kolodny, "Timing Optimization in Logic with Interconnect," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 19 – 26, April 2008. ppt
  • R. Dobkin, A. Morgenshtein, A. Kolodny, R. Ginosar, "Parallel vs. Serial On-Chip Communication," SLIP 2008, Newcastle, UK, April 2008. ppt
  • Z. Guz, I. Keidar, A. Kolodny, and U. Weiser, "Utilizing Shared Data in Chip Multiprocessors with the Nahalal Architecture,"  20th ACM Symp. on Parallelism in Algorithms and Architectures (SPAA'08), special track on Hardware and Software Techniques to Improve the Programmability of Multicore Machines, June 2008. (SPAA Best Paper Award).   pdf   ppt
  • K. Moiseev, A. Kolodny and S. Wimer, "Wire Spacing, Planar Graphs and the Minimization of Dynamic Power in VLSI Microprocessors," VLSI-SOC 2008. pdf
  • I. Vaisband, E. Friedman, R. Ginosar and A. Kolodny, "Power Efficient Tree-Based Crosslinks for Skew Reduction," GLSVLSI 2009. pdf
  • Y. Aizik and A. Kolodny, "Exploration of Energy-Delay Tradeoffs in Digital Circuit Design,"  IEEEI 2008. pdf
  • R. Beraha, I. Walter, I. Cidon and A. Kolodny, "The Design of a Latency Constrained, Power Optimized NoC for a 4G SoC", NOCS 2009, San Diego, CA, May 2009.
  • R. Manevich, I. Walter, I. Cidon and A. Kolodny, "Best of Both Worlds: A Bus-Enhanced NoC (BENoC)", NOCS 2009, San Diego, CA, May 2009. pdf
  • E. Krimer, M. Erez, I. Keslassy, A. Kolodny and I. Walter, "Packet-Level Static Timing Analysis for NoCs", NOCS 2009, San Diego, CA, May 2009. pdf
  • I. Walter, I. Cidon, and A. Kolodny, D. Sigalov, "The Era of Many-Modules SoC: Revisiting the NoC Mapping Problem", Second International Workshop on Network on Chip Architectures (NoCArc), 2010.
  • Y. Ben-Itzhak, I. Cidon, and A. Kolodny, "Performance and Power Aware CMP Thread Allocation Modeling", International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2010), January 2010. pdf
  • I. Walter, I. Cidon, and A. Kolodny, D. Sigalov, " Leveraging Application-Level Requirements in The Design of a NoC for a 4G SoC – a Case Study", DATE 2010. pdf
  • S. Beer, R. Ginosar, R. and A. Kolodny, "The Devolution of Synchronizers", ASYNC 2010. pdf
  • A. Abdel-hadi, E.G. Friedman, R. Ginosar and A. Kolodny, " Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 15 – 20, May 2010.  pdf
  • Z. Guz, O. Itzhak, I. Kediar. A. Kolodny, A. Mendelson and U.C. Weiser, "Threads vs. Caches: Modeling the Behavior of Parallel Workloads", ICCD 2010.  pdf
  • T. Morad, A.Kolodny and U.C. Weiser, "Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors", PAAP 2010. pdf
  • R. Manevich, I. Cidon, A. Kolodny and I.Walter, "best of both worlds: A Bus Enhanced NoC", IEEEI 2010.
  • S. Kvatinsky,   E. G. Friedman , A. Kolodny  and  L. Schächter, "Power Grid Analysis Based on a Macro Circuits Model", IEEEI 2010. pdf
  • G. Sizikov, E.G. Friedman, A. Kolodny and M. Zelikson, Frequency Dependent Efficiency Model of On-Chip DC-DC Buck Converters", IEEEI 2010. pdf
  • G. Sizikov, E.G. Friedman, A. Kolodny and M. Zelikson, "Efficiency Optimization of Integrated DC-DC Buck Converters," ICECS 2010. pdf
  • T.Y. Morad, A. Kolodny and U.C. Weiser, “Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors,” PAAP 2010. pdf
  • Y. Ben-itzhak, I. Cidon and A. Kolodny, "Delay Analysis of Wormhole Based Heterogeneous NoC,"   NOCS 2011. pdf
  • S. Beer, R. Ginosar, M. Priel, R. Dobkin, A. Kolodny, “An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm”,  ISCAS 2011. pdf
  • Y. Ben-Itzhak, E. Zahavi, I. Cidon and A. Kolodny, “NoCs simulation framework for OMNeT++”, NOCS 2011. pdf
  • S. Kvatinsky, E.G. Friedman, A. Kolodny and U. C. Weiser,”Memristor-based IMPLY Logic Design Procedure,” ICCD 2011. pdf
  • R. Manevich, I.Cidon,A. Kolodny, I. Walter and S. Wimer, “Centralized Adaptive Routing for NoCs,” EUROMICRO Conference on Digital System Design – DSD 2011. pdf
  • Y. Ben-Itzhak, E. Zahavi, I. Cidon and A. Kolodny, “HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs,” submitted to DATE 2012. pdf
  • R. Malits, E. Bolotin, A. Kolodny and A. Mendelson, “Exploring the Limits of GPGPU Scheduling,” HiPEAC 2012pdf
  • Y. Ben-itzhak, I. Cidon and A. Kolodny , “Optimizing Heterogeneous NoC Design,” SLIP 2012. pdf 
  • R. Manevich, I. Cidon, and A. Kolodny, "Handling Global Traffic in Future CMP NoCs", SLIP 2012. pdf
  • S. Kvatinsky, E.G. Friedman, A. Kolodny and U. C. Weiser , "MRL – Memristor Ratioed Logic", CNNA 2012. pdf
  • S. Kvatinsky, E.G. Friedman, A. Kolodny and U. C. Weiser , “The Desired Memristor for Circuit Designers,” Frontiers in Electronic Materials conference, Germany, June 2012. pdf
  • S. Kvatinsky, K. Talisveyberg, D. Fliter, E. G. Friedman, A.Kolodny and U.C. Weiser,  "Models of Memristors for SPICE Simulations," IEEEI  2012. pdf
  • I. Vaisband, E. G. Friedman, R. Ginosar, A. Kolodny, "Energy metrics for power efficient crosslink and mesh topologies",  ISCAS 2012 pdf
  • R. Manevich, I. Cidon and A. Kolodny,  "Dynamic Traffic Distribution Among Hierarchy Levels in Hierarchical Networks-on-Chip", NOCS 2013. pdf
  • R. Manevich, L. Polishuk, I. Cidon and A. Kolodny, "Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip", EUROMICRO Conference on Digital System Design – DSD 2013. pdf
  • R. Manevich, S. Rehana, O. Turgeman and A. Kolodny, "ViLoCoN – An Ultra Lightweight Lossless VLSI Video Codec for NoC", SOCC 2013. pdf
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memory Intensive Computing," Proceeding of the Annual Non-Volatile Memories Workshop, March 2014. pdf
  • O. Itzhak, I. Keidar, A. Kolodny and U. Weiser, “Performance scalability and dynamic behavior of Parsec benchmarks on many-core processors,” SFMA 2014 pdf
  •  S. Kvatinsky, Y. H. Nacson, R. Patel, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristive Multistate Pipeline Register," Proceedings of the International Cellular Nanoscale Networks and their Applications, July 2014. pdf
  • E. Zahavi, I. Keslassy, and A. Kolodny, “Quasi Fat Trees for Utility Clusters and their Fault-Resilient Closed-Form Routing,” Hot Interconnects, 2014. pdf 
  • E. Zahavi, O. Rottenstreich, A. Shpiner, I. Keslassy and A. Kolodny,  "Links as a Service (LaaS): Feeling Alone on the Shared Cloud", ANCS 2016.